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M62384FP
8-Bit, 4-Channel, 3 to 5 V D-A Converter (Buffered)
REJ03F0077-0100Z Rev.1.0 Sep.19.2003
Description
The M62384 is a CMOS-structure semiconductor integrated circuit incorporating four 8-bit D-A converter channels with output buffer op-amps. Serial data transfer type input can easily be used through a combination of three lines: DI, CLK, and LD. Outputs incorporate buffer op-amps that have a drive capacity of 1 mA or above for both sink and source, and can operate over the entire voltage range from almost ground to VCC (0 to 5 V), making peripheral elements unnecessary and enabling configuration of a system with few component parts. Support of power supply voltages of 3 V to 5 V enables the M62384 to be used in a wide range of applications.
Features
* 12-bit serial data input (3-line type: SDI, SCK, SLD) * Serial data transfer clock frequency: 10 MHz (max.) * Output buffer op-amps Operable over entire voltage range from almost ground to VCC * Power-on reset and external reset functions * Chip select function Up to 4 chips connectable on the same bus * Supported power supply voltage: 3 V to 5 V (2.7 V to 5.5 V)
Application
Signal gain setting and automatic adjustment in CTV and display monitors, conversion from digital data to analog data in consumer and industrial products
Pin Connection Diagram (Top View)
GND 1 Ao1 Ao2 Vref Ao3 Ao4
2 3 16 CS1 15 CS0 14 RST 13 VDD 12 SCK 11 SDI 10 SLD 9
M62384FP
VCC 4
5 6 7
GND 8
VSS
Package: 16P2N
This product is currently under development, and specifications and other details may be modified at a future date.
Rev.1.0, Sep.19.2003, page 1 of 8
M62384FP
Block Diagram
SDI 11 SCK 12 VDD 13
12-bit shift register
RST 14
Power-on reset
8
Channel decoder
10 SLD 16 CS1 15 CS0
VSS 9
8-bit latch 8-bit D-A
8-bit latch 8-bit D-A
8-bit latch 8-bit D-A
8-bit latch 8-bit D-A
1 GND
Vref
5
VCC 4
2 Ao1
3 Ao2
6 Ao3
7 Ao4
Rev.1.0, Sep.19.2003, page 2 of 8
M62384FP
Pin Functions
Pin No. 1, 8 2 3 6 7 4 5 9 10 Symbol GND Ao1 Ao2 Ao3 Ao4 Vcc Vref Vss SLD Analog power supply (3 V to 5 V) Must rise simultaneously with VDD or after VDD rise. D-A converter upper reference voltage input pin Digital GND Serial load signal input pin (Schmitt trigger input: with input hysteresis) When SLD is high, data is loaded from shift register into 8-bit latch corresponding to address. Serial data input pin (TTL input in case of 5 V power supply) Inputs serial data with a 12-bit data length (MSB-first). Serial clock signal input pin (Schmitt trigger input: with input hysteresis) At rising edge, data is read into shift register one bit at a time. Digital power supply pin (3 V to 5 V) When power supply rises, D-A output is reset (0 V output: power-on reset). Forced reset pin (TTL input in case of 5 V power supply) L: D-A output (AO1 to 4) = Fixed setting of 0 V H: Reset release (power-on reset operation) Chip select pins (TTL input in case of 5 V power supply) Access possible only when chip select data (D11, D10) and pin (CS1, CS0) logic match. Function Analog GND: analog circuit GND (D-A converter lower reference voltage) D-A converter output pins (ch1 to ch4): full-swing buffer output Output voltage: Ao (00)h = 0V, Ao (FF)h = 255/256 x VREF
11 12 13 14
SDI SCK VDD RST
15 16
CS0 CS1
Absolute Maximum Ratings
(Unless specified otherwise, Ta = 25C)
Item Power supply voltage Digital input voltage Reference voltage input voltage D-A output voltage Permissible loss Operating ambient temperature Storage temperature Symbol VCC,VDD VDIN Vref VAO Pd Topr Tstg Rated Value -0.3 to 7.0 -0.3 to Vcc+0.3 ( 7.0) -0.3 to Vcc+0.3 ( 7.0) -0.3 to Vcc+0.3 ( 7.0) 300 -20 to +75 -40 to +125 Unit V V V V mW C C DC voltage ("H" level) Conditions
Rev.1.0, Sep.19.2003, page 3 of 8
M62384FP
Recommended Operating Conditions
(Unless specified otherwise, VCC = VDD = 5 V 10%, Vref = 2 V to VCC, VSS = GND = 0 V, fsck = 5 MHz, VDINH = VDD, VDINL = VSS, Ta = 20C to 75C)
Specification Values Item Analog power supply voltage Digital power supply voltage Reference voltage Serial clock frequency "H" level digital input voltage "L" level digital input voltage Clock "H" pulse width Clock "L" pulse width Clock rise time Clock fall time Data setup time Data hold time Load setup time Load hold time Load "H" pulse width Reset "L" pulse width Load setup time after reset release Symbol VCC VDD Vref fsck VDINH VDINL tsckH tsckL tsckR tsckF tDCH tCHD tCHL tLDC tLDH tRSTL tRCHL 10 20 40 20 20 50 50 Min. 2.7 2.7 2.0 0.5VDD VSS 30 30 200 200 Typ. Max. 5.5 5.5 5.5 10 VDD 0.2VDD Unit V V V MHz V V ns ns ns ns ns ns ns ns ns ns ns VCC = VDD 2.7V VCC = VDD 2.7V Test Conditions VCC = VDD VCC = VDD Vref VCC
Timing Chart
tSCKR tSCKH t SCKF
SCK
tSCKL
SDI
t LDC t DCH t CHD t CHL t LDH
SLD
tRCHL t LDD
RST
t RSTL
AO
Rev.1.0, Sep.19.2003, page 4 of 8
M62384FP
Electrical Characteristics
(Unless specified otherwise, VCC = VDD = 5 V 10%, Vref = 2 V to VCC, VSS = GND = 0 V, fsck = 5 MHz, VDINH = VDD, VDINL = VSS, Ta = 20C to 75C) (1) Digital block
Specification Values Item Digital block circuit current Input leakage current Input threshold voltage Input hysteresis voltage Symbol IDD IDINLK VDINT VDINT -10 0.2VDD 0 100 Min. Typ. Max. 1.0 10 0.5VDD Unit mA A V mV VDIN = VSS to VDD Test Conditions
(2) Analog block
Specification Values Item Analog block circuit current Reference voltage input current Differential nonlinearity error Nonlinearity error Zero scale error Full-scale error Output current Settling time Symbol ICC Iref SDL SNL SZERO SFULL IAO tLDD -1.0 -1.5 -2.0 -2.0 0.5 5 Min. Typ. 0.8 0.5 Max. 2.0 1.0 1.0 1.5 2.0 2.0 10 Unit mA mA LSB LSB LSB LSB mA S Test Conditions No load All channels: Maximum current conditions VCC = VDD = 2.7V to 5.5V IA0: With no load
VOA = 0.1V to VCC - 0.1V VOA = 0.54.5V, IOA = 0.1mA, Co = 50pF output absorbed within 0.5 LSB VCC = 0 V 5 V, V0A = 0 V setting voltage (reference values)
Power-on reset voltage
VPR
0.8
1.5
2.5
V
Digital Data Format
MSB(First) D11 D10 D9 D8 D7 D6 D5 D4 DAC data D3 D2 D1 LSB D0
Chip select data Address data
(1) Chip select data
D11 0 0 1 1 D10 0 1 0 1 CS1 L L H H CS0 L H L H
Data is transferred only when logic of D11 and D10 matches CS pin setting (CS1, CS0).
Rev.1.0, Sep.19.2003, page 5 of 8
M62384FP (2) Address data
D8 0 0 1 1 D9 0 1 0 1 Channel Selection AO1 selected AO2 selected AO3 selected AO4 selected
DAC Data
D7 0 0 0 0 D6 0 0 0 0 D5 0 0 0 0 D4 0 0 0 0 D3 0 0 0 0 D2 0 0 0 0 D1 0 0 1 1 D0 0 1 0 1 D-A output (0/256)xVref (1/256)xVref (2/256)xVref (3/256)xVref

1 1
1 1
1 1
1 1
1 1
1 1
1 1
0 1
(254/256)xVref (255/256)xVref
Data Timing Chart
SDI D11 D10 D9 D8 D2 D1 D0
SCK
SLD
Ao When SLD is high, data captured in the shift register is loaded into the 8-bit latch corresponding to the address. Therefore, SCK should be held high or low when SLD is high.
Rev.1.0, Sep.19.2003, page 6 of 8
M62384FP
Sample Application Circuit
SDI SCK MCU SLD RST
RST SLD SCK SDI
VCC VDD
VCC VDD Ao1 Ao2 Ao3
Vref
Chip select setting (connected to either VDD or GND)
Vref CS0 CS1 GND
Ao4
GND
VSS
M62384FP
Rev.1.0, Sep.19.2003, page 7 of 8
M62384FP
16P2N-A
JEDEC Code -- e b2 Weight(g) 0.2 Lead Material Cu Alloy
MMP
Plastic 16pin 300mil SOP
EIAJ Package Code SOP16-P-300-1.27
Package Dimensions
16
9
HE
E
L1
L
Rev.1.0, Sep.19.2003, page 8 of 8
e1
Recommended Mount Pad Symbol
1 8
F A
G
D
A2
b
A1
x
M
e y
A A1 A2 b c D E e HE L L1 z Z1 x y c
z Detail G Detail F
Z1
b2 e1 I2
Dimension in Millimeters Min Nom Max 2.1 0.2 0.1 0 -- 1.8 -- 0.5 0.4 0.35 0.25 0.2 0.18 10.2 10.1 10.0 5.4 5.3 5.2 -- 1.27 -- 8.1 7.8 7.5 0.8 0.6 0.4 -- 1.25 -- -- 0.605 -- -- 0.755 -- -- 0.25 -- 0.1 -- -- 0 -- 8 -- 0.76 -- -- 7.62 -- -- 1.27 --
I2
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